In order to meet the challenge of Moore's law, Intel has succeeded in reducing the feature size of its transistors to increase the speed of its devices. Intel started mass production of microprocessors with a feature size of less than 100nm in 2000, thus entering the era of nanotechnology. However, it is apparent that conventional feature size reduction, or scaling, can only take us so far with current materials and processes before we hit a wall at sub-10nm feature sizes. At this point, 'equivalent' scaling of devices through nanotechnology will emerge as the driving force behind Moore's Law. As part of its contribution to CRANN, Intel Ireland has provided five staff to the centre who are engaged in nanotechnology research. Peter Gleeson, Matt Shaw and Chris Murray work as Researchers-in-Residence based in TCD and UCC. Jenny Patterson is the Nanotechnology Program Manager. The products Intel Ireland manufacture in ten years will be based on fundamental research carried out today. Intel's involvement in CRANN is both recognition of the excellent research work underway in Irish universities and a commitment to add value to Intel Ireland through the groundbreaking application of nanotechnology.
Intel Ireland is the largest industrial partner in the CRANN project. Intel has been manufacturing various logic and memory products at its state of the art Irish fabs for over a decade. By successfully shrinking transistor size, we have been able to satisfy Moore's law which predicts computing density will double every two years. In order to continue to meet this aggressive roadmap, Intel recognizes the need for more advanced materials and processing capabilities in the coming years which go beyond 'conventional CMOS'. Nanotechnology in general offers many potential solutions to these future requirements. How can the incredible properties of novel materials such as nanotubes or nanowires be employed in our devices? Can we use templated self assembly to 'grow' nanoscale structures in place rather than use expensive lithographic techniques? Can the spin of the electron be used to switch a transistor more effectively than its charge at sub-10nm gate lengths? These important questions are being addressed by the three individual research projects being carried out by the Intel Researchers in Residence within CRANN. These Intel employees work within the university research groups, learning the theory and techniques necessary to make progress on the issues and providing an 'industrial' view on applications and requirements. One successful outcome of this relationship so far is the information exchange between the university groups and Intel's Materials Analysis labs. Another important outcome has been the realization of substrates from the 'Adaptive Grid' project. This project is truly multi-disciplinary in nature and aims to identify and overcome key challenges associated with the integration of top-down and bottom-up fabrication of processor type architectures, with a near-term focus in enabling the benchmarking of a range of nano-materials (e.g. materials formed by different process methods). To date expertise has been combined from the scientists in CRANN, with designers and fabrication engineers, integrators, and technicians in Intel Ireland to realise the first revision of a silicon substrate which will allow much more reliable testing of materials such as carbon nanotubes. This will provide a huge research advantage to CRANN for enhancements in place ability, contact ability, testability, and reproducibility of measurements.
Intel Ireland's participation in CRANN is both a commitment to nanotech solutions to future industry needs and recognition of the outstanding research work being carried out in Irish universities. Leonard Hobbs, overall Manager of Silicon Research at Intel Ireland says "Intel is delighted to have been involved in the CRANN team from the start. We recognise the unique advantage of collaborating with world class researchers in an area of strategic importance to our business and we look forward to continued success in collaborating with this international research institute."
The Intel Researchers-in-Residence
Jenny Patterson - Nanotechnology Program Manager
Jenny Patterson has been working at Intel for the past 6 years and holds the position of Nanotechnology Program Manager for Intel Ireland. Jenny is responsible for managing Intel Ireland's nanotechnology research initiatives in Ireland and Europe. Jenny manages Intel's interests in CRANN, a joint Industry-Academia Centre for Research on Adaptive Nanodevices and Nanostructures. Within CRANN, Intel staff perform fundamental scientific research on self-assembly, nanocontacting, and spintronics. In addition, Jenny oversees Intel Ireland's 6th and 7th EU framework activities in the area of nano-materials and nanoelectronics. Jenny transferred to her current role from Intel Ireland's Business Development Group in 2003; her role there was to identify and drive research opportunities for Intel in Ireland focusing on nanotechnology. Jenny originally joined Intel Ireland in 2001 as a Process Engineer for the 0.25 um and 0.18 um CVD manufacturing processes. Before joining Intel, Jenny worked in the National Microelectronics Research Centre (NMRC, now Tyndall National Institute) as Business Development Manager for the Microsystems Group. This work focused on commercialisation of existing MEMS based technology and devices, and further development of application driven uTAS (Total Analysis Systems) research. Jenny also previously worked for Bourns Inc., Microelectronics Division, as Engineering Project Leader working on new product development programs for electronic components, notably, environmental sensors, Thin Film on Silicon micro-inductors, and chip scale packaged passives. Prior to joining Bourns Inc., Jenny led the Plating Group, Interconnection & Packaging, at NMRC in commercially driven solar cell, passive component, and IC metallisation research and development. Jenny received a B.Sc. (Chemistry) and M.Sc. from University College, Cork.
Chris Murray - Researcher-in-Residence
Chris Murray joined CRANN in September 2004 as an Intel Researcher-in-Residence under the guidance of Prof. Mike Coey. He is working towards the demonstration of spintronic functionality in silicon-based devices. Previously he has been working with Intel Fab24 for over 3 years as Senior Process Engineer in the CVD module, 2 years of which were spent in Portland Technology Development, Oregon. Prior to that, he worked as a research assistant in the field of mesoporous silica low-k dielectrics at the Technical University of Chemnitz, Saxony, Germany. He also spent 4 years at the NMRC, Cork, Ireland researching magnetic materials and novel applications. In college he carried out short projects on magnetic thin films with Sony Applied Magnetic Research Labs, Tokyo and Thomson Central Research Labs, Paris. He has a B.A. in Science of Materials and M.Sc. in Physics (Hard Magnetic Materials), both from Trinity College Dublin. He has authored over 15 publications.
Matt Shaw - Researcher-in-Residence
Matt Shaw joined CRANN in August 2004 as an Intel Researcher-in-Residence under the guidance of Prof. Michael A. Morris in UCC. His current research interests include polymer templating and self-assembly processes to be used in the making of ordered arrays of nano-materials (wires, tubes etc.) with a view to integrating into functional novel transistor devices. He previously spent 11 years at Intel Ireland as a Senior Process Engineer working in the area of High Density Plasma CVD of low k dielectrics used in logic and flash technology processes. During his time at Intel he also spent 3 years working on CVD process development and transfer from Intel U.S R&D facilities to Intel Ireland. Matt was also a Defect Reduction Engineer for his first 3 years in Intel. His technical expertise includes many areas of CVD processing including vacuum systems, RF power systems, gas delivery and monitoring hardware, robotics, parts cleaning, transducers and sensors, and clean room technology. Matt has extensive knowledge of Semiconductor High Volume manufacturing equipment and people systems (Maintenance, Taskforces, Technology integration issues etc.).He has a B.Sc. in Applied Physics and Microelectronics (1991 DCU) and an M.Sc. in Physics (1993 DCU) in the spectroscopy of laser plasma XUV light sources. He has authored 12 publications. A very interesting aspect of Matt’s work is the Adaptive Grid Substrate project. This involves getting industry engineers from Intel and the PI’s and researchers from CRANN to work together to design and fabricate silicon test substrates for research use in CRANN. These substrates allow CRANN to be at forefront of nanoscience and enable Intel to facilitate the research community to carry out research potentially relevant to the ICT sector.
Peter Gleeson - Researcher-in-Residence
Peter has worked in the process engineering department of Intel Ireland since Nov 2003, and he joined the CRANN Institute as a researcher in residence in March 2006, where he is working on electrical contacting and characterization of nanowire based materials. Prior to joining Intel, he worked as a deposition / etch engineer for Hewlett-Packard and Agilent Technologies in their semiconductor fabrication facilities in the UK, where he was responsible for process development and technology transfer to manufacturing sites in the UK and Asia. Before he moved to industry, Peter spent seven years working on the development of high frequency compound semiconductor devices at the Tyndall National Institute. He has authored four publications, and holds a B.Sc. (Physics) from the University of Essex, UK.
INTEL
Intel Ireland is the largest industrial partner in the CRANN project. Intel has been manufacturing various logic and memory products at its state of the art Irish fabs for over a decade. By successfully shrinking transistor size, we have been able to satisfy Moore's law which predicts computing density will double every two years. In order to continue to meet this aggressive roadmap, Intel recognizes the need for more advanced materials and processing capabilities in the coming years which go beyond 'conventional CMOS'. Nanotechnology in general offers many potential solutions to these future requirements. How can the incredible properties of novel materials such as nanotubes or nanowires be employed in our devices? Can we use templated self assembly to 'grow' nanoscale structures in place rather than use expensive lithographic techniques? Can the spin of the electron be used to switch a transistor more effectively than its charge at sub-10nm gate lengths? These important questions are being addressed by the three individual research projects being carried out by the Intel Researchers in Residence within CRANN. These Intel employees work within the university research groups, learning the theory and techniques necessary to make progress on the issues and providing an 'industrial' view on applications and requirements. One successful outcome of this relationship so far is the information exchange between the university groups and Intel's Materials Analysis labs. Another important outcome has been the realization of substrates from the 'Adaptive Grid' project. This project is truly multi-disciplinary in nature and aims to identify and overcome key challenges associated with the integration of top-down and bottom-up fabrication of processor type architectures, with a near-term focus in enabling the benchmarking of a range of nano-materials (e.g. materials formed by different process methods). To date expertise has been combined from the scientists in CRANN, with designers and fabrication engineers, integrators, and technicians in Intel Ireland to realise the first revision of a silicon substrate which will allow much more reliable testing of materials such as carbon nanotubes. This will provide a huge research advantage to CRANN for enhancements in place ability, contact ability, testability, and reproducibility of measurements.
Intel Ireland's participation in CRANN is both a commitment to nanotech solutions to future industry needs and recognition of the outstanding research work being carried out in Irish universities. Leonard Hobbs, overall Manager of Silicon Research at Intel Ireland says "Intel is delighted to have been involved in the CRANN team from the start. We recognise the unique advantage of collaborating with world class researchers in an area of strategic importance to our business and we look forward to continued success in collaborating with this international research institute."
Intel Ireland is the largest industrial partner in the CRANN project. Intel has been manufacturing various logic and memory products at its state of the art Irish fabs for over a decade. By successfully shrinking transistor size, we have been able to satisfy Moore's law which predicts computing density will double every two years. In order to continue to meet this aggressive roadmap, Intel recognizes the need for more advanced materials and processing capabilities in the coming years which go beyond 'conventional CMOS'. Nanotechnology in general offers many potential solutions to these future requirements. How can the incredible properties of novel materials such as nanotubes or nanowires be employed in our devices? Can we use templated self assembly to 'grow' nanoscale structures in place rather than use expensive lithographic techniques? Can the spin of the electron be used to switch a transistor more effectively than its charge at sub-10nm gate lengths? These important questions are being addressed by the three individual research projects being carried out by the Intel Researchers in Residence within CRANN. These Intel employees work within the university research groups, learning the theory and techniques necessary to make progress on the issues and providing an 'industrial' view on applications and requirements. One successful outcome of this relationship so far is the information exchange between the university groups and Intel's Materials Analysis labs. Another important outcome has been the realization of substrates from the 'Adaptive Grid' project. This project is truly multi-disciplinary in nature and aims to identify and overcome key challenges associated with the integration of top-down and bottom-up fabrication of processor type architectures, with a near-term focus in enabling the benchmarking of a range of nano-materials (e.g. materials formed by different process methods). To date expertise has been combined from the scientists in CRANN, with designers and fabrication engineers, integrators, and technicians in Intel Ireland to realise the first revision of a silicon substrate which will allow much more reliable testing of materials such as carbon nanotubes. This will provide a huge research advantage to CRANN for enhancements in place ability, contact ability, testability, and reproducibility of measurements.
Intel Ireland's participation in CRANN is both a commitment to nanotech solutions to future industry needs and recognition of the outstanding research work being carried out in Irish universities. Leonard Hobbs, overall Manager of Silicon Research at Intel Ireland says "Intel is delighted to have been involved in the CRANN team from the start. We recognise the unique advantage of collaborating with world class researchers in an area of strategic importance to our business and we look forward to continued success in collaborating with this international research institute."
The Intel Researchers-in-Residence
Jenny Patterson - Nanotechnology Program Manager
Jenny Patterson has been working at Intel for the past 6 years and holds the position of Nanotechnology Program Manager for Intel Ireland. Jenny is responsible for managing Intel Ireland's nanotechnology research initiatives in Ireland and Europe. Jenny manages Intel's interests in CRANN, a joint Industry-Academia Centre for Research on Adaptive Nanodevices and Nanostructures. Within CRANN, Intel staff perform fundamental scientific research on self-assembly, nanocontacting, and spintronics. In addition, Jenny oversees Intel Ireland's 6th and 7th EU framework activities in the area of nano-materials and nanoelectronics. Jenny transferred to her current role from Intel Ireland's Business Development Group in 2003; her role there was to identify and drive research opportunities for Intel in Ireland focusing on nanotechnology. Jenny originally joined Intel Ireland in 2001 as a Process Engineer for the 0.25 um and 0.18 um CVD manufacturing processes. Before joining Intel, Jenny worked in the National Microelectronics Research Centre (NMRC, now Tyndall National Institute) as Business Development Manager for the Microsystems Group. This work focused on commercialisation of existing MEMS based technology and devices, and further development of application driven uTAS (Total Analysis Systems) research. Jenny also previously worked for Bourns Inc., Microelectronics Division, as Engineering Project Leader working on new product development programs for electronic components, notably, environmental sensors, Thin Film on Silicon micro-inductors, and chip scale packaged passives. Prior to joining Bourns Inc., Jenny led the Plating Group, Interconnection & Packaging, at NMRC in commercially driven solar cell, passive component, and IC metallisation research and development. Jenny received a B.Sc. (Chemistry) and M.Sc. from University College, Cork.
Chris Murray - Researcher-in-Residence
Chris Murray joined CRANN in September 2004 as an Intel Researcher-in-Residence under the guidance of Prof. Mike Coey. He is working towards the demonstration of spintronic functionality in silicon-based devices. Previously he has been working with Intel Fab24 for over 3 years as Senior Process Engineer in the CVD module, 2 years of which were spent in Portland Technology Development, Oregon. Prior to that, he worked as a research assistant in the field of mesoporous silica low-k dielectrics at the Technical University of Chemnitz, Saxony, Germany. He also spent 4 years at the NMRC, Cork, Ireland researching magnetic materials and novel applications. In college he carried out short projects on magnetic thin films with Sony Applied Magnetic Research Labs, Tokyo and Thomson Central Research Labs, Paris. He has a B.A. in Science of Materials and M.Sc. in Physics (Hard Magnetic Materials), both from Trinity College Dublin. He has authored over 15 publications.
Matt Shaw - Researcher-in-Residence
Matt Shaw joined CRANN in August 2004 as an Intel Researcher-in-Residence under the guidance of Prof. Michael A. Morris in UCC. His current research interests include polymer templating and self-assembly processes to be used in the making of ordered arrays of nano-materials (wires, tubes etc.) with a view to integrating into functional novel transistor devices. He previously spent 11 years at Intel Ireland as a Senior Process Engineer working in the area of High Density Plasma CVD of low k dielectrics used in logic and flash technology processes. During his time at Intel he also spent 3 years working on CVD process development and transfer from Intel U.S R&D facilities to Intel Ireland. Matt was also a Defect Reduction Engineer for his first 3 years in Intel. His technical expertise includes many areas of CVD processing including vacuum systems, RF power systems, gas delivery and monitoring hardware, robotics, parts cleaning, transducers and sensors, and clean room technology. Matt has extensive knowledge of Semiconductor High Volume manufacturing equipment and people systems (Maintenance, Taskforces, Technology integration issues etc.).He has a B.Sc. in Applied Physics and Microelectronics (1991 DCU) and an M.Sc. in Physics (1993 DCU) in the spectroscopy of laser plasma XUV light sources. He has authored 12 publications. A very interesting aspect of Matt’s work is the Adaptive Grid Substrate project. This involves getting industry engineers from Intel and the PI’s and researchers from CRANN to work together to design and fabricate silicon test substrates for research use in CRANN. These substrates allow CRANN to be at forefront of nanoscience and enable Intel to facilitate the research community to carry out research potentially relevant to the ICT sector.
Peter Gleeson - Researcher-in-Residence
Peter has worked in the process engineering department of Intel Ireland since Nov 2003, and he joined the CRANN Institute as a researcher in residence in March 2006, where he is working on electrical contacting and characterization of nanowire based materials. Prior to joining Intel, he worked as a deposition / etch engineer for Hewlett-Packard and Agilent Technologies in their semiconductor fabrication facilities in the UK, where he was responsible for process development and technology transfer to manufacturing sites in the UK and Asia. Before he moved to industry, Peter spent seven years working on the development of high frequency compound semiconductor devices at the Tyndall National Institute. He has authored four publications, and holds a B.Sc. (Physics) from the University of Essex, UK.
INTEL
Intel Ireland is the largest industrial partner in the CRANN project. Intel has been manufacturing various logic and memory products at its state of the art Irish fabs for over a decade. By successfully shrinking transistor size, we have been able to satisfy Moore's law which predicts computing density will double every two years. In order to continue to meet this aggressive roadmap, Intel recognizes the need for more advanced materials and processing capabilities in the coming years which go beyond 'conventional CMOS'. Nanotechnology in general offers many potential solutions to these future requirements. How can the incredible properties of novel materials such as nanotubes or nanowires be employed in our devices? Can we use templated self assembly to 'grow' nanoscale structures in place rather than use expensive lithographic techniques? Can the spin of the electron be used to switch a transistor more effectively than its charge at sub-10nm gate lengths? These important questions are being addressed by the three individual research projects being carried out by the Intel Researchers in Residence within CRANN. These Intel employees work within the university research groups, learning the theory and techniques necessary to make progress on the issues and providing an 'industrial' view on applications and requirements. One successful outcome of this relationship so far is the information exchange between the university groups and Intel's Materials Analysis labs. Another important outcome has been the realization of substrates from the 'Adaptive Grid' project. This project is truly multi-disciplinary in nature and aims to identify and overcome key challenges associated with the integration of top-down and bottom-up fabrication of processor type architectures, with a near-term focus in enabling the benchmarking of a range of nano-materials (e.g. materials formed by different process methods). To date expertise has been combined from the scientists in CRANN, with designers and fabrication engineers, integrators, and technicians in Intel Ireland to realise the first revision of a silicon substrate which will allow much more reliable testing of materials such as carbon nanotubes. This will provide a huge research advantage to CRANN for enhancements in place ability, contact ability, testability, and reproducibility of measurements.
Intel Ireland's participation in CRANN is both a commitment to nanotech solutions to future industry needs and recognition of the outstanding research work being carried out in Irish universities. Leonard Hobbs, overall Manager of Silicon Research at Intel Ireland says "Intel is delighted to have been involved in the CRANN team from the start. We recognise the unique advantage of collaborating with world class researchers in an area of strategic importance to our business and we look forward to continued success in collaborating with this international research institute."
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